The present invention relates generally to folded cascode amplifiers and, more particularly, to fully complementary folded cascode amplifiers with low supply current to peak output current ratios.
In switched capacitor circuits, a signal is first sampled as a voltage onto a capacitor on one phase of a non-overlapping driving clock, and then delivered as a charge to an integrator on the opposite clock phase. As charge is delivered to an integrator, the integrator output must settle within an acceptable time limit before the end of the clock phase or an error in the charge transfer results. Often, to reduce the effects of external noise within a switched capacitor system, a differential signal is sampled into two capacitors and delivered to a fully differential amplifier that is configured as an integrator with two feedback capacitors. A traditional folded cascode amplifier is often used in this application, as it settles quickly, often requires no additional compensation, and has high open loop gain.
The traditional folded cascode amplifier is illustrated schematically in FIG. 1, constructed with CMOS technology. In this configuration, complementary current sources act upon the output. NMOS devices N0, N2, N1 and N3 pull the outputs out+ and out- toward ground, while PMOS devices P3, P5, P4 and P6 pull the outputs out+ and out- toward the supply voltage. The polarity of the current sources is affected by the differential currents of a differential input device pair P0, P1. Devices P0 and P1 proportion current sourced by devices P2 and P7 to the junctions between the N type current sources depending on the differential voltage input across input terminals in+ and in-, thereby reducing the amount of current available from the N type current sources to the output terminals out+ and out-. A bias generator (not shown) generates fixed bias voltages Vb1, Vb2, Vb3, and Vb4 to ensure that the currents through the devices are appropriate, and all devices operate in their saturation region. The bias voltages are adjusted by the bias generator so the outputs always remain within an acceptable output common mode voltage range.
In operation, devices N0 and N1 are scaled and biased so each conducts two units of current, while devices P3 and P4 are biased to conduct one unit each. The differential input devices P0 and P1 are supplied with two units of current from device P2, which is biased to conduct two units of current. Under steady state conditions, with zero differential input voltage, these two units of current are equally distributed to N0 and N1 so that the currents through cascode devices P5, P6, N2, and N3 are each one unit of current, and the total supply current is four units. Under these conditions, no current flows to the output terminals out+ and out-.
When a large differential input voltage is applied to input terminals in+ and in-, the differential input devices P0 and P1 become unbalanced. In the most extreme case, the full two units of current from device P2 are diverted to only one of the N type current sources. For example, if the voltage on terminal in+ is very much more positive than the voltage on terminal in-, the two units of current from device P2 are diverted through device P1 and device N0 to ground. Thus, output terminal out+ is supplied with one current unit from device P3, but is not pulled low because no current flows through device N2. Output terminal out-, on the other hand, is pulled high by current source P4 at one current unit and low by device N3 at two current units, resulting in a net current of one current unit toward ground. Output terminal out+, on the other hand, is supplied with one current unit from device P3, but is not pulled low because no current flows through device N0. Thus, output terminal out+ outputs one current unit while, as noted, the amplifier is supplied by four current units. Excluding the supply current requirements of the bias generating circuitry, the supply current to peak output current ratio, then, is four to one.
A four-to-one supply current to peak output current ratio, however, can be inefficient for high performance applications. In such applications, it is desirable to have a high signal to noise ratio (SNR) and often for the circuit to support a high clock frequency. As discussed in more detail below, however, satisfying either of these design criteria requires increasing the peak output current of the amplifier. In amplifiers with a large supply current to peak output current ratio, however, a proportional increase in supply current accompanies even a modest increase in peak output current. This results in undesirable increases in power and dissipation requirements.
The SNR of switched capacitor circuits is the ratio of the input charge magnitude to the input charge noise. The input charge magnitude (q.sub.in) after the input phase is complete is given by: EQU q.sub.in =C.sub.in *V.sub.in
where C.sub.in is the total input capacitance and V.sub.in is the input voltage. The noise properties of switched capacitor circuits can be shown to be dominated by the folded thermal noise of the switches. The input charge noise (q.sub.n,input) is given by: EQU q.sub.n,input =(2KTC.sub.in).sup.0.5
where:
K=Boltzman's constant, and PA1 T=absolute temperature. PA1 Thus, the SNR is: EQU SNR=q.sub.in /q.sub.n,input =V.sub.in (C.sub.in /2KT).sup.0.5.
It is clear from this equation that an increase in the input capacitance values results in an increased signal to noise ratio.
An increase in input capacitance values, however, increases the settling time of the circuit, thus reducing the speed at which the circuit can be clocked. The settling time (t.sub.st) of a well designed integrator stage is essentially composed of two parts: an initial slew period (t.sub.slew), where the differential input voltage is significantly greater than the differential input pair's linear operating range, and a final time constant period (t.sub.tc), where the output asymptotically approaches it's final settled state: EQU t.sub.st =t.sub.slew +t.sub.tc.
The initial slew period is controlled by the input charge magnitude (q.sub.ni) and amplifier peak output current (I.sub.pkout). Excluding the output stray capacitance, the initial slew period (t.sub.slew) can be approximated by the following equation: EQU t.sub.slew =q.sub.in /I.sub.pkout.
The final time constant period (t.sub.tc) is controlled by amplifier input differential device transconductance (gm.sub.iput pair) and output load capacitance (C.sub.load). The following equation gives a practical approximation: EQU t.sub.tc =C.sub.load /gm.sub.input pair.
From these equations, it is clear that the final time constant period is minimized by simply increasing the transconductance of the input differential pair. The slew period, however, which is increased by an increase in input capacitance values, can only be reduced by increasing the peak output current of the amplifier. But, as noted at the outset, an increase in the peak output current results in a large increase in supply current in circuits with high supply current to peak output current ratios.
In light of the foregoing, there is a need for a fully complementary cascode amplifier with a decreased supply current to peak output current ratio.